MOS忆阻器混合逻辑门设计及其在逻辑综合中的应用
esign of Small Area Hybrid CMOS Memristor Logic
忆阻器可用于逻辑电路设计，以减小逻辑电路的面积。本文在多输入与门、或门、与非门、或非门等基本逻辑门的基础上，进一步设计出新型复合逻辑门。这些新型逻辑门具有面积小、能够级联等优点。本文将这些新型逻辑门融入于开源的标准工艺库中。基于此新的工艺库，使用DC工具对逻辑电路进行逻辑综合，以此来评估新型逻辑门在减小逻辑电路面积方面的潜力。选取ISCAS85和ISCAS89系列中的较大规模电路作为实验对象，实验结果显示，比对传统的CMOS设计，使用新型逻辑门能够显著减小标准电路的面积，平均减小28.97%。?
Memristor can be used to design a logic circuit with a small area. This paper first designs some basic and compound logic gates using both CMOS transistors and memristors, which have small area, and direct cascade features. After that, we evaluate the area of designed logic gate using Design Compiler of Synopsis by open cell library modification. Results for larger ISCAS'85 and ISCAS'89 benchmark circuits show that the proposed designs achieved about 28.97% reduction in area compared to those in CMOS designs.
尤志强、胡智鹏
微电子学、集成电路电子电路半导体技术
忆阻器逻辑门工艺库工具逻辑综合
Memristorlogic gatesProcess libraryDesign CompilerSynthesis
尤志强,胡智鹏.MOS忆阻器混合逻辑门设计及其在逻辑综合中的应用[EB/OL].(2015-12-01)[2025-08-21].http://www.paper.edu.cn/releasepaper/content/201512-73.点此复制
评论