65纳米工艺下低功耗高线性度音频ΣΔ 模数转换器的研究与实现
Research and Implementation of A Low-power High-linearity Audio ΣΔ ADC In 65nm Process
综述文章：本论文设计了一款适合音频应用的低功耗、高线性度ΣΔ ADC。此 ADC包含了高性能2-1级联单比特量化ΣΔ 调制器和采用ROM、RAM设计的低功耗，高面积利用率数字抽取滤波器。此款ADC芯片采用中芯国际 65 nm 1P8M混合信号CMOS制作工艺，核心面积为 0.581 平方毫米。测试结果表明，本文设计的ΣΔ ADC在 22.05 kHz的音频带宽内，采样频率为5M Hz时最高信噪失真比可达 90 dB，动态范围为 93 dB，在 1.2 V供电电压下功耗为 2.2 mW，同时实现了高性能与低功耗。
We designed an audio ΣΔ ADC which has low power consumption and high linearity. The proposed ΣΔ ADC contains a 2-1 cascaded 1- bit ΣΔ modulator and a low-power, area-efficient digital decimation filter which is designed using RAM and ROM. This chip has been implemented in SMIC 65nm mixed-signal 1P8M CMOS standard silicon process, and the die area is 0.581 mm2. Experiment results shown that 90 dB signal to noise plus distortion ratio (SNDR) and 93 dB dynamic range (DR) are achieved within 22.05 kHz audio band, at 5 M Hz sample rate. The ADC's power dissipation is 2.2 mW under 1.2 V supply voltage, which means that this chip obtains high-performance and low-power at the same time.
曹天霖、孙颖、梁国、韩雁、廖璐、罗豪
微电子学、集成电路
ΣΔ ADC低功耗高线性度音频应用
sigma-delta ADClow-powerhigh-linearityaudio applications
曹天霖,孙颖,梁国,韩雁,廖璐,罗豪.65纳米工艺下低功耗高线性度音频ΣΔ 模数转换器的研究与实现[EB/OL].(2013-02-01)[2025-08-18].http://www.paper.edu.cn/releasepaper/content/201302-10.点此复制
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