亚10nm技术代垂直沟道围栅纳米线器件多阈值设计
Multi-VT Design of Vertical Channel Nanowire FET for Sub-10nm Technology Node
本文提出了一种针对垂直沟道围栅纳米线场效应晶体管的多阈值调节技术，通过TCAD（计算机辅助设计软件）仿真手段将非对称halo（环状）掺杂技术和纳米线直径设计相结合，以此实现三种不同阈值的围栅纳米线器件。仿真结果表明，相比在器件的漏端附近引入halo掺杂，在源极附近引入halo能够实现范围更宽的阈值电压调节和更好的短沟道效应控制。而且通过仿真发现，仅调整源端halo的掺杂浓度和纳米线的直径这两个器件参数，即可实现7nm技术节点上至少三种不同的阈值电压方案，由此可见，垂直沟道的围栅纳米线器件将十分适合在大规模SoC（片上系统）中进行应用。
In this work, a feasible multi-VT modulation strategy in vertical nanowire FETs (VNWFETs) combining asymmetric halo doping with nanowire diameter is proposed and verified by TCAD simulation. The results show that halo configuration close to source side exhibits larger VT-tuning range and better SCE controlling. Moreover, adjustment of halo doping concentration and nanowire diameters can be adopted to provide at least three VT choices for 7nm technology node. It is demonstrated that VNWFETs is quite promising for SOC application.
黎明、陈珙
微电子学、集成电路半导体技术
微电子学垂直纳米线非对称结构多阈值环状掺杂
microelectronicsvertical nanowireasymmetric configurationmulti- VThalo doping
黎明,陈珙.亚10nm技术代垂直沟道围栅纳米线器件多阈值设计[EB/OL].(2017-04-28)[2025-08-14].http://www.paper.edu.cn/releasepaper/content/201704-821.点此复制
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