SPI总线的VerilogHDL实现
the realization of SPI based on VerilogHDL
本文根据m序列的生成原理，利用硬件描述语言Verilog HDL在QuartusII平台上生成m序列，同时根据SPI总线协议，设计了具有16位寄存器的主机与从机的环形结构。由于m序列具有良好的伪随机特性，本文在Modelsim仿真环境下利用m序列验证了SPI总线设计的正确性。?????
ccording to the principle of m-sequence generating, this paper focus on the realization of m sequences based on the software QuartusII with the hardware language VerilogHDL. At the same time, we designed 16-bit register for the ring structure of SPI abide by the protocol of it. Finally we verified the correctness of design by the simulation environment of Modelsim with m-sequence which had a good pseudo-random characteristic.
陈宗义
微电子学、集成电路电子电路
m序列VerilogHDLSPI
m-sequenceVerilogHDLSPI
陈宗义.SPI总线的VerilogHDL实现[EB/OL].(2010-11-17)[2025-05-01].http://www.paper.edu.cn/releasepaper/content/201011-402.点此复制
评论